Virtex 5 announced

Two slices per CLB, four 6-LUTs + 4 FFs per slice. A LUT can be
configured as a RAM64 or SRL32. But a CLB can only have 4 RAMs or SRLs
(similar to SLICEL / SLICEM). DSP blocks have a 25x18 multiplier
(useful for 32-bit floating point). Block RAMs are 36 kbits.

Press release says engineering samples of LX50, lX85, LX110 are
shipping now.


LX50:
7,200 slices (actual slices, CLB array 120*30)
48 BRAMs (each 36kbits, total 1728 kbits)
48 DSP
FF324, FF676, FF1153


LX85:
12,960 slices
96 BRAMs
48 DSP
FF676, FF1153


LX110:
17,280 slices
129 BRAMs
64 DSP
FF676, FF1153, FF1760


Press release
http://www.xilinx.com/prs_rls/2006/silicon_vir/0658lxship.htm


Slice schematics, some timing numbers and performance figures (PDF)
http://www.xilinx.com/bvdocs/whitepapers/wp245.pdf


Product table, (slice/bram/dsp/io counts for each LX-series part) (PDF)
http://www.xilinx.com/products/silicon_solutions/fpgas/virtex/virtex5...


Comparison with Virtex-4
http://www.xilinx.com/products/silicon_solutions/fpgas/virtex/virtex5...